The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and device for self-aligned etching. Merely by way of example, the invention has been applied to the manufacturing of devices with decreased critical dimensions (e.g., devices characterized by channel lengths of less than 135 nanometers or even smaller). As an example, the invention can be used for the process of forming floating control gates on semiconductor devices. But it would be recognized that the invention has a much broader range of applicability. For example, an embodiment of the present invention can be used for the manufacturing of flash devices.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. Most recently, various processes have been for the fabrication of integrated circuits. For example, self-aligned source (SAS) etching process, which has been develop to, among other things, enable lithography with higher definition, has been developed and widely used for the fabrication of integrated circuits with decreased size (e.g., 90 nanometer or 65 nanometer device). While processes such as self-aligned source etching enable smaller IC to be manufactured and lithography to be performed with higher resolution as compared to earlier techniques, these processes are often inadequate for various applications.
Therefore, an improved technique for processing semiconductor devices is desired.